Analysis of Quantization Noise and Power Estimation of Continuous-Time Delta Sigma Analog-to-Digital Converter Using Test Enable Feature For 4G Radios

ABSTRACT


INTRODUCTION
Radio recurrence (RF) and mixed-signal topologies are fundamental components in future remote applications such as wireless 4G radios [1]. This type of innovation could enable the remote interchanges frameworks to relocate and help multiband and multi-standard radios, RF front-end/back-end, and advanced baseband systems. The drivers for mobile wireless communications are standards and protocols, frequency bands, power consumption, size, and cost [2]. This paper addresses the different issues in the design of future software radios 4G and 5G with emphasis on optimized power and test enable feature of oversampling analog-to-digital converters (ADCs) [3]. We have tried to review the challenges imposed on the wireless receiver design by the low-power specifications and small size in mobile terminals. The sigma-delta modulator structures that can conceivably be utilized for executing ADCs for portable remote radios are displayed in the point of view of a CMOS usage [4].
Generally, in modern luxury car, we have a cellular phone, fax, GPS receiver, television or even an internet browser in addition to radio. All these portable wireless communication systems use receivers to get the information signals from the world. The signals are received by an antenna, and the desired signal band, for example a GSM channel, is selected from the total received spectrum [5]. This frequency band undergoes analog filtering, amplification, frequency modulation and analog-to-digital conversion. Further signal processing is done in the digital domain by a digital signal processor. Figure 1 shows Generic block diagram of wireless receiver which consists of an antenna, an RF/IF (Intermediate frequency) front-end, an ADC, and a digital signal processor (DSP) [6].

Figure 1. Generic Block diagram of Wireless Receiver
The ADC is used to digitize an RF, IF, or baseband signal depending on the receiver design. The location of the ADC in a receiver chain is very important that affects the overall performance, complexity, power dissipation, size, and cost [7]. The filtering and frequency translation are performed in digital domain, which reduces the complexity of the receiver and increases the flexibility. A flexible receiver consists of a digitally controlled analog front-end software-defined radio and a programmable digital back-end. The digital back-end forms the signals and feeds back control signals that reconfigures between different standards or dynamically within the same standard, the building blocks in the front-end. These blocks switch to a different set of performance values a different filter order or cut-off frequency for a filter, or a different gain and bandwidth for a low-noise amplifier, or a different gain for a variable gain amplifier, or different dynamic range and bandwidth for an ADC, etc [8]. Important tenors in the receiver design for wireless portable applications are: smaller product sizes, moderate products and longer stand-by times.
Products can be made smaller and cheaper by increasing the level of integration. Wireless communication has revolutionized everyone's lives by enabling a high speed connection directly to the people/information customers needs [12]. Wireless technologies such as 3G (third generation) and other such technologies coexist and work synergistically to meet customer needs. This requires different wireless systems that further needs multimode, multiband, and multi-standard mobile terminals. Sharing and/or switching building blocks is important requirement to extend the battery life and/or to reduce cost [9,10]. Flexibility and adaptability are the key features in a multimode, multiband, and multi-standard wireless radio [11].

RESEARCH METHOD 2.1 System Level Modeling and Analysis of CT DSM Architecture as (DUT) for 4G Radio Application
Versatile sigma delta ADC configuration is shown in Figure 2, which consist of forward path coefficient b1, b2, b3 and integrator coefficient a1, a2, a3, a4 along with two digital to analog converter (DAC) DAC1 and DAC 2 and 2 bit quantizer for multi-mode structure in 5MHz, 7MHz and 10MHz channel information exchange limits. It is a reconfigurable and programmable ADCs which covers a perfect world an information exchange limit run to upgrade power and range for a specific application, by using the same ADC structures, re-use and plan strategies. Continuous time sigma-delta (CT ΣΔ) ADCs are used as a piece of remote correspondences, where a high information transmission at low power uses is required. Despite the fact that CT ΣΔ ADC offers the probability to change over high transmission limit data with a ridiculous low power usage. Table 1 gives the details about different modes of CT sigma delta ADC. In this table for

GUI of Noise Calculation CT Sigma Delta ADC Used for 4G Radio
There are different types of noise signals in the circuit affecting power and the errors are addressed by the system or circuit level techniques. This reduces the noise less than 25 percent of original present. When we calculate thermal noise and the clock jitter noise, it is around 75 percent of the total noise. GUI is designed for the noise calculation of the modulator. The delay is reduced or compensated by using a fast path around the quantizer which is used in the modulator. Using fully differential architecture is used; the mismatch in the rise and fall edge of the DAC output can be reduced. Figure 3 shows the results that are obtained after executing using MATLAB. For different values of all the parameters, different values of bandwidth and power are obtained as Lc , Nc and OSR.  Figure 4 shows the power consumption of CT sigma delta ADC for 4G Radio. For the calculation of power consumption the different parameters are there on which the overall power consumption depends is represent in GUI block. The analog supply voltage plays a vital role in it for calculation of power in CT sigma delta ADC.

- Modulator ADC for Test Enable Feature for Wireless
A test enable feature of CT A/D is proposed introducing the test signal generation (TSG) and CORDIC for evaluating the performance of ADC to address the challenge of 4G and upcoming 5G wireless radio. System level plan of a delta-sigma modulator ADC for 4G radios is presented. Figure 5 shows block diagram of proposed - modulator ADC with test enable capability.

Test Stimulus generation and power estimation of TSG
A simulink model of TSG is shown in Figure 6 which generates a sinusoidal signal which is required in subsequent stages of ADC as a test signal in ADC. Ramp signal is also required to test INL and DNL performance of ADC, which can be taken from test signal generated by TSG after converting in to ramp signal. Digital resolution based lossless (LDI) discrete integrator is used as TSG [2]. The resonators are obtained by cascading to integrator which, can be seen in Figure 6. The sinusoidal signal is generated while considering the variation in the coefficient a12 and a21 and the value of x1 and x2 fixed as a21=2 -6 ; a12= 2.667×10 -4 ;x1(0) = 0 ; x2(0) = 0.0327159 and fos= 3.063MHz .
Power consumption of TSG is written as: Where PINT_delay=power of integer delay; PMultiplier= power of Multiplier unit and PAdder=power of adder unit.   Table 3 shows extracted noise parameters of CT ADCs used for 4G radio which in Band Noise (IBN) is depends on choice of bits size, availably of Bandwidth (BW), order of modulator (Lc). Table 4 shows extracted power of CT sigma delta ADC which is technology depends on power supply (Vdd) and other parameter also for 4G radio. ADC works in different modes and in each mode power optimization is needed. The GUI based noise and power estimation is modeled to meet this requirement with enabling the test feature of ADC used in wireless receiver.

RESULTS AND ANALYSIS
Tabulated result it is notice that minimum power dissipation Pct=3.06mw is achieved when Lc=3,Nc=4,OSR=10,BW=25 MHz.

CONCLUSION
This paper discusses power productivity of various delta sigma modulator topologies used in wireless application. Power and noise estimation techniques are designed and simulated to exact the power utilization of the delta sigma modulator. The test enable features are modeled and simulated in MATLAB simulink environment for CT sigma delta ADC used in 4G radios. In this work quantization noise and other parameter are reduced significantly that were not addressed in similar research works.