Simulation of PCI Express™ Transaction Layer Using Hardware Description Language

Abstract

PCI Express is a high-speed serial connection that operates more like a network than a bus. PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms. PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper  analyze and simulates the function of Transaction layer IP core in the System Level with top-down design method, wrote the codes to implement Transaction Layer using Very high speed hardware description language (VHDL) and provided the simulation results using Active HDL Simulation tool. The simulation result shows that the designed IP core meets the required protocol specifications for the proper functioning of PCI Express Transaction layer.