180 nm NMOS voltage-controlled oscillator for phase-locked loop applications

Abstract

The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a total harmonic distortion (THD) of 3.9%. The proposed design is verified by PSpice simulations. A new criterion is proposed for optimizing NMOS LC oscillators.