Design and Implementation of High Speed-Low Power Compressors as standard cells for ASIC’s

kommu chaitanya


The 3-2, 4-2, 5-2 find many applications in the evolution of integrated circuits. One of the major applications of them is to add partial products that are generated at one stage in Multipliers. In this paper a newly proposed 3-2, 4-2, 5-2 architectures having less delay and reduced power consumption than the conventional architectures are presented. The key idea of designing these multipliers with better performance characteristics leads to the implementation of pass transistors, transmission gates and domino logic circuits. All the CMOS circuits used in proposed architectures are having better performances than their existing CMOS counterparts. The proposed 3-2 model offer 66.6-82.69% less power and 52.48-64.62% reduction in propagation delay than the conventional 3-2 model. The proposed 4-2 model offer 52.37-55.367% less delay and 7.8-16.86% reduction in propagation delay than the conventional 4-2 model. The proposed 5-2 model offer 54.93-57.4% less power and 9.2-74.82% reduction in propagation delay. With all these significance improvements in their performance, they are chosen as a best option in designing Multipliers.

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